One driving factor behind the push for low power design is the growing class of personal computing and communications devices that demand complex functions at high speed and low power to enable them to be supplied by existing power supplies. Another driving fact is that excessive power consumption has become a limiting factor in integrating more transistors on a single chip. Unless power consumption is dramatically reduced, the resulting heat will limit the feasible packing and performance of VLSI circuits and systems.
One method of reducing power consumption that has been recently proposed is to employ multiple supply voltages. The authors of Chang, J. M. and Pedram, M., "Energy Minimization Using Multiple Supply Voltages," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 4, December 1997 ("Chang") describe a scheduling technique that assigns each operation in a data flow graph (DFG) to one of a fixed set of different supply voltages in order to minimize power consumption while meeting a predefined set of timing or throughput (for pipelined data paths) constraints. This technique starts from a high level description of the DFG and its output is a mapping of the optimized DFG onto a set of register transfer level (RTL) or data path operators (adders, multipliers, etc.) that have been previously characterized so as to get the power-timing tradeoff curves. In that sense the approach certainly belongs to the class of behavioral synthesis algorithms, and hence does not address the key issues of how to provide the multiple supply voltage rails on the chip with significantly penalizing the available routing resources.
A second approach is discussed in Kuroda, T. et al., "Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design," IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998 ("Kuroda"). The approach in Kuroda is based on generating a mockup of the critical path of the design (actually two different replicas of the critical path, respectively 3% faster and slower). A built-in suite of test data are then transferred through the critical path mockups between register pairs that are clocked with the main clock of the system, and the output is compared with the output of a directly connected pair of registers. The result is used to feed a counter and eventually a voltage regulator that generates the supply voltage for the actual chip. Although the supply voltage is adaptively regulated to settle at its optimal (lowest) value V.sub.DD * using a local feedback loop, only one supply voltage is employed. As a result, a large portion of the system may still be fed with a supply voltage in excess of that required for complete operation within a clock cycle.
A third approach is discussed in Usami, K et al., "Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor," IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998 ("Usami"). The technique in Usami applies a multiple supply voltage scheme to the synthesis, placement, and routing of RTL blocks. The authors in Usami assume that two different levels of supply voltage are available on the chip: V.sub.DD.sup.H and V.sub.DD.sup.L. During the technology mapping phase, each cell of a block is supplied at whichever one of the two different supply voltage levels minimizes the number of level shifters (required to convert from cells supplied with V.sub.DD.sup.L to cells supplied with V.sub.DD.sup.H. As in Chang, this approach is geared toward the front end of the design process, and thus, must employ an oversimplified model of the timing and power consumed by the cells. Also, because cells within the same hierarchical block can be assigned to different supply voltages, routing resources are severely penalized because of the other tracks that are necessary to distribute the extra supply rail. In addition, only two different supply voltages (V.sub.DD.sup.H and V.sub.DD.sup.L) are considered.